Metal insulator metal (MIM) capacitors are made of a bottom metal layer and an upper metal layer and an insulator layer that is positioned between these two metal layers.
Metallization layers of CMOS back-end may serve as bottom metal layers while the upper metal layer can be a subsequent metallization layer of CMOS or can be formed as a separate upper metal layer.
The capacitance of an MIM capacitor can be increased by using an insulator layer that is made of a high relative permittivity (dielectric constant) material (high k material). The quality of an insulator layer may be responsive to the smoothness and to the cleanliness of the bottom metal layer.
Trench (three dimensional) MIM capacitors better utilize the foot space of an integrated circuit allowing producing the capacitor with the maximum capacitance density but the manufacturing process of trench MIM capacitor encounters the reliability problems.
One of these problems is connected with the necessity of introducing a gap (or recess) between the upper edges of the bottom and the upper metal layers located in the trench. During the recess processing of a gap (or recess) the bottom metal layer of the trench MIM capacitor is exposed to aggressive etch treatment. This results in a rugged and unclean surface of the bottom metal layer and affects the insulator quality.
U.S. Pat. No. 6,436,787 of Wong-Cheng Shin et al. titled “Method of forming Crown-type MIM capacitor integrated with the Cu damascene process” describes a method for fabricating a three dimensional MIM capacitor in a copper damascene process. This MIM capacitor has no recess of any electrodes composing the stacked capacitor. As a result there are strong overshoots of the electric field at the device edge which limits the reliability performance of the device (the field is enhanced due to the electrode edge curvature effect and small distance between the electrodes).
U.S. Pat. No. 7,224,014 of Hideo Ichimura titled “Semiconductor device and method for fabricating the same” describes a method for fabricating a trench DRAM capacitor in an intermetal dielectric (IMD) module. This method suggests forming a recess of the lower polysilicon electrode. The recess of the polysilicon layer composing the lower electrode of the stacked trench capacitor is formed by anisotropic dry etching of a polysilicon layer using the resist in the trench as a mask. The deposition of the polysilicon layer is associated with high temperatures (about 640 Celsius) and may not be fitted for various manufacturing processes. This method does not allow the precise control of the penetration depth into the lower polysilicon layer in the process of the recess formation.
U.S. Pat. No. 7,927,959 of Steven J. Keating et al. titled “Method of patterning a metal on a vertical sidewall of excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby” describes a method for fabricating MIM capacitor for the manufacturing eDRAM device. The method includes filling an excavated feature with a filling material such that a portion of the metal on vertical sidewalls (lower electrode) is exposed above the material. A first etch chemistry etches the exposed portion of the metal away and produces recess while a second wet etch chemistry removes the material from the excavated feature. This method suffers from lower electrode height variation (recess amount) which causes significant capacitance variation of the MIM capacitor. Furthermore, the surface of the lower electrode after the material removal requires an additional clean which further reduces the quality of the lower electrode interface with the further deposited dielectric layer. Accordingly—this process will result in a reduced reliability of the MIM capacitor.
There is a growing need to provide a reliable method for manufacturing high quality trench MIM capacitors.